Patent Abstracts of Japan Publication No. 08213606 (published Aug. 20, 1996) describes a lateral high breakdown strength MOSFET having an n+ substrate. German publication No. 4325804 A1 describes a process for producing high-resistance SiC from low-resistance SiC starting material. U.S. Pat. No. 5,611,955 describes a high resistivity silicon carbide substrate for use in semiconductor devices. U.S. Pat. No. 5,378,912 describes a lateral semiconductor-on-insulator (SOI) device.
One object of the present invention is to provide devices which allow blocking of very high voltages without the need for a very thick drift region which must be grown by epitaxy.
Another object of the present invention is to provide a lateral power device structure, such as a very high voltage (greater than 1000 v up to and greater than 10000 v) power switching device, fabricated on a junction-isolated or semi-insulating substrate in a wide bandgap semiconductor having a breakdown field substantially greater than silicon.
Another object of the present invention is to provide such lateral power devices in the form of a lateral metal oxide semiconductor field effect transistor (MOSFET) or lateral insulated gate bipolar transistor (IGBT) on silicon carbide.
Accordingly, one preferred embodiment of the invention provides a lateral power device structure fabricated in an epilayer (epitaxially-grown layer) on a semi-insulating substrate, especially a semi-insulating silicon carbide substrate. Such a semi-insulating substrate can be achieved, for instance, by doping, e.g., with vanadium or similar dopant materials. The preferred devices include a semi-insulating silicon carbide substrate, and an epitaxially grown drift region (e.g., Nxe2x88x92) adjacent the semi-insulating substrate (e.g., doped at a level of about 2-5xc3x971015 cmxe2x88x923). A lateral semiconductor device, e.g., an insulated gate field effect transistor (or MOSFET) or IGBT is provided in the epilayer. Such devices include generally source and drain regions (e.g., both N+), an insulating layer (e.g., SiO2), and a gate, e.g., formed of polysilicon. Other conventional semiconductor device features can also be included, as those skilled in the art will appreciate.
Additional objects, embodiments, and features of the invention will be apparent from the following description, and the drawings appended hereto.